1. Field of the Invention
The present invention relates to a power supply and a method for adjusting delay parameters thereof, and more particularly to a technique having multiple built-in delay parameter combinations in a controller of a full bridge phase shifted power supply with synchronous rectification and current doubler and dynamically applying the delay parameter combinations in accordance with the loading conditions.
2. Description of the Related Art
With reference to FIG. 5, a conventional full bridge phase shifted power supply with synchronous rectification and current doubler has a transformer T1, a phase shifted full bridge converter 70 and a synchronous rectification and current doubler circuit 80. The phase shifted full bridge converter 70 is connected with the primary side of the transformer T1. The synchronous rectification current doubler circuit 80 is connected with the secondary side of the transformer T1.
The phase shifted full bridge converter 70 has a top switch QA on the leading leg, a bottom switch on the leading leg QB, a top switch on the lagging leg QC and a bottom switch on the lagging leg QD. The synchronous rectification and current doubler circuit 80 has a top rectification switch Q1, a bottom rectification switch Q2 and two output inductors L1 and L2. The top switch QA on the leading leg QA, the bottom switch on a leading leg QB, the top switch on a lagging leg QC, the bottom switch on a lagging leg QD, the top rectification switch Q1 and the bottom rectification switch Q2 are formed by MOSFETs. The gates GA, GB, GC, SR1 and SR2 are connected to a controller U1 and switched by the controller U1.
The top switch on the leading leg QA and the bottom switch on the lagging leg QD, and the bottom switch on the leading leg QB and the top switch on the lagging leg QC are alternatively turned on in pairs. For example, when the top switch on the leading leg QA and the bottom switch on the lagging leg QD are turned on, an induced positive voltage is generated by the secondary side of the transformer T1. Meanwhile, the top rectification switch Q1 is turned off, and the bottom rectification switch Q2 is turned on. The output inductors L1 and L2 are respectively formed in two current paths, and current of the secondary side of the transformer T1 is equal to current flowing through the output inductor L1, which is one half of an output current. The other half of output current is provided by the output inductor L2 to constitute a current doubler according to the flywheel effect.
The top rectification switch Q1 and the bottom rectification switch Q2 of the synchronous rectification and current doubler circuit 80 are driven in collaboration with the top switch QA on the leading leg and the bottom switch on the leading leg QB. Here is an example for driving the bottom rectification switch Q2.
With reference to FIG. 6, a driving signal applied to the gate SR2 of the bottom rectification switch Q2 is shown. The waveform of the driving signal is identical to that applied to the gate GA of the top switch on the leading leg QA. In other words, the signal (GA) driving the top switch QA on the leading leg can be used to drive the bottom rectification switch Q2. When the bottom rectification switch Q2 is turned off and the top rectification switch Q1 is turned on, a dead time should be added. However, circulating current is forced to pass through a body diode of the turned off bottom rectification switch Q2 during the dead time. IQ2 represents a current passing through the bottom rectification switch Q2. Slash portions prior to transitions represent current passing through the body diode of the bottom rectification switch Q2 when Q2 is turned off. Current passing through the body diode of a turned off switch can damage the switch and further lowers an operating efficiency of the power supply.
Another method driving the top rectification switch Q1 and the bottom rectification switch Q2 is described in the following (still using the example of driving the bottom rectification switch Q2). With reference to FIG. 7, such method applies a result of a logical operation “OR” of the driving signals GA and GD to drive the bottom rectification switch Q2. Under the circumstance, current passing through the body diode of Q2 before Q2 transitions from an off state to an on state can be reduced. However, current passing through the body diode of Q2 before Q2 transitions from an on state to an off state still exists and thus damages Q2 and affects an operating efficiency of the power supply accordingly.
It can be seen from the aforementioned two driving methods that circulating current passes through the body diode of Q2 when Q2 is turned off, and the second method prolongs the time that Q2 is turned on or makes rising edges at transition ahead of time. The second method further associates with a change of delay parameters.
As discussed, when the top rectification switch Q1 and the bottom rectification switch Q2 are driven by the second method, current does not pass through the body diode of Q1 and Q2 before Q1 and Q2 transition from the off state to the on state. However, the second method is not applicable for driving Q1 and Q2 under all circumstances. With reference to FIG. 8, a characteristic curve illustrating loads and operating efficiencies of a full bridge phase shifted power supply with synchronous rectification and current doubler is shown. The horizontal axis represents loads applied to the full bridge phase shifted power supply, is expressed by percentage, and is divided into three zones, namely 0˜30% for the first zone, 30%˜80% for the second zone, and 80% and up for the third zone. The vertical axis represents operating efficiencies of the full bridge phase shifted power supply. M1 is a characteristic curve generated by using the first method to drive the synchronous rectification and current doubler circuit 80, and M2 is a characteristic curve generated by using the second method to drive the synchronous rectification and current doubler circuit 80. It is noted that the operating efficiencies using the first driving method are better than those using the second driving method when subjected to loads being less than 30%, while the operating efficiencies using the second driving method are better than those using the first driving method when subjected to loads being 80% and up.
From the foregoing comparison, the delay parameters associated with Q1 and Q2 of the synchronous rectification and current doubler circuit 80 affect the operating efficiency of the power supply in a certain degree or even according to an interaction effect. Therefore, how to adjust the delay parameters to enhance the operating efficiency of the power supply needs to be further explored to find a feasible solution.